Course syllabus
Course-PM
EEN195 Applied design of power electronics on printed circuit boards lp2 HT26 (7.5 hp) CourseSyllabus_EEN195_2026_V8.pdf
Course is offered by the department of Electrical Engineering
Contact details
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Function |
Name |
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Contact info |
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Examiner |
Stefan Lundberg |
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Lecturers |
Linhua Lai |
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Fredrik Larsson |
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Stefan Lundberg |
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Vaishnavi Ravi |
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Tutorial assistants |
Linhua Lai |
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Lakshmi Priya Gandla |
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Laboratory and Project assistants |
Linhua Lai |
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| Vaishnavi Ravi | |||
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Lakshmi Priya Gandla |
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Course purpose
The purpose with the course is to develop competence for the complete design process for a system of power electronics, a board power system, with advanced and complex loads in a limited product. The design process starts from the requirements/product knowledge and ends with a final assembled product, a physical product with a design that is based on the life cycle requirements of the product. This includes protective circuits/components, EMI filter, how primary and secondary converters form a board power system in a DC supplied system, how different optimizations influence the performance of the final product while still fulfilling the requirements, how different blocks works together as a highly efficient board power system and how different stage and design constraints forms the final product.
Schedule
Course literature
Lecture notes and handouts will be available on Canvas.
Course design
The prerequisite for this course is the course ENM061 - Power electronic converters or equivalent together with either ENM071 - Applied power electronics: Devices and implementations or DAT096 - Embedded system design project. This means that the course is continuing to build on the theory covered in these courses and it will be assumed that the students have followed the courses or have equivalent knowledge.
The course is designed around a practical project in which student groups follow the complete design process of a power electronic converter: Requirements → Calculation → Component selection → Schematic → PCB layout → PCB parasitics → Simulation → Manufacturing → Measurement → Verification. Lectures, tutorials, computer labs, guest lectures and practical labs support the relevant project stage. The project is documented in one cumulative report that is extended at each hand-in. Earlier sections shall be updated when later calculations, component choices, design reviews, simulations or measurements affect previous assumptions.
The students will perform the complete design process from idea to verification measurements on the assembled design. The design work includes block design, analytical dimensioning, circuit-level simulation, component selection based on real design parameters and tolerances, schematic capture, PCB layout, analytical estimation of switching-loop inductance, PCB-level parasitic simulation, thermal calculations, practical EMI design, transient protection, producibility and testability. Students shall plan verification from the requirements and compare calculated, simulated and measured results. Technical lifetime and MTBF shall be considered as design inputs and evaluated for the final design.
As can be seen in the teaching plan below there are:
18 lectures = 36 h
1 tutorials = 2 h
6 computer labs = 12 h
8 practical labs = 16 h
6 online help session = 2h
1 presentation = 4 h
1 oral exam = 1h
TOTAL: 73 h
This leaves 127 h for own work time, which means that you need to work on your own outside scheduled hours.
Teaching plan:
Linhua Lai LL in the teaching plan Contact info.
Fredrik Larsson FL in the teaching plan Contact info.
Stefan Lundberg SL in the teaching plan Contact info.
Lakshmi Priya Gandla LP in the teaching plan
Vaishnavi Ravi VR in the teaching plan Contact info.
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Study week, Date, Time |
Description / Material |
Teacher |
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1 (45) Tue 3/11 13-14 |
Lecture 1: Course and project introduction. Introduce the complete engineering flow and the cumulative report structure. |
SL |
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1 (45) Tue 3/11 14-17 |
Lecture 2: Setting requirements, specifications and verification criteria for a design. |
FL |
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1 (45) Thu 5/11 13-15 |
Lecture 3: Requirements decomposition, operating conditions, power budget and traceability to verification. |
FL |
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1 (45) Thu 5/11 15-17 |
Lecture 4: Power-converter design flow, analytical calculations and engineering tools. Distinguish dimensioning tools, circuit simulation, PCB design and later PCB-level simulation. |
FL |
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1 (45) Fri 6/11 13-15 |
Computer lab 1: Introduction to the project tools and the cumulative report workflow. |
PI/LL |
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2 (46) Mon 9/11 12:00 |
Deadline hand-in 1: Project requirements and specifications, requirement IDs, preliminary verification criteria and Writing quiz. |
FL/LL |
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2 (46) Tue 10/11 13-15 |
Lecture 5: Reflections on requirement hand in and Guest lecture Würth Elektronik – from calculated values to real component design parameters: inductance, Isat, Irms, DCR, capacitor DC bias, ESR/ESL, ripple current, temperature, tolerances, derating and packages. |
FL/Würth |
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2 (46) Tue 10/11 15-17 |
Lecture 6: Guest lecture Würth Elektronik – robust component selection and application of component design parameters in the converter. |
FL/Würth |
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2 (46) Thu 12/11 13-16 |
Tutorial 1: Dimensioning the converter and translating calculated values into critical component requirements. |
VR |
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2 (46) Thu 12/11 16-17 |
Lecture 7: Circuit simulation to support component dimensioning and schematic design (in computer room). |
VR/LL |
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2 (46) Fri 13/11 13-15 |
Computer lab 2: Support with circuit calculations, preliminary component selection, schematic capture and correct footprints. |
PI/LL/VR |
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3 (47) Mon 16/11 12:00 |
Deadline hand-in 2: Converter dimensioning, initial circuit simulation and Schematic Version 1. Include all components, correct packages/footprints, critical component design parameters and preliminary component choices; final values are not yet required. |
FL/LL |
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3 (47) Tue 17/11 13-15 |
Lecture 8: From schematic to physical PCB – floorplan, stack-up, placement, power paths, return paths, decoupling, vias and thermal paths. |
FL |
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3 (47) Tue 17/11 15-17 |
Lecture 9: Switching current loops and PCB parasitics – commutation loop, gate-drive loop, switch node, loop area, L·di/dt, overshoot, ringing and EMI. |
FL |
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3 (47) Thu 19/11 13-15 |
Lecture 10: PCB/EMC design – return-current continuity, reference planes, coupling, filtering, switch-node control and layout implementation. |
FL |
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3 (47) Thu 19/11 15-17 |
Lecture 11: PCB parasitic estimation and workshop – identify the switching loop and analytically estimate loop inductance and expected overshoot for the group design. |
FL |
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3 (47) Fri 20/11 13-15 |
Computer lab 3: Support with PCB floorplan, current paths, switch-loop identification and PCB Layout Version 1. |
LL/VR |
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4 (48) Mon 23/11 12:00 |
Deadline hand-in 3: PCB Layout Version 1 with correct packages/footprints and test points. Include annotated current/return paths, identified switch loop, analytical loop-inductance estimate, predicted L·di/dt overshoot. The three identified risks connected to the code of ethics for engineers module in Chapter 11 of the report. |
FL/LL |
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4 (48) Tue 24/11 13-15 |
Lecture 12: PCB production, soldering, chemical products, assembly constraints and manufacturing release. |
SL |
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4 (48) Tue 24/11 15-17 |
Lecture 13: PCB Design Review Workshop part 1 Group-based design review and discussion. The eight project groups work in pairs in breakout rooms to review each other´s designs. Each group reviews component choices, PCB layout, critical current paths, switching loop, estimated parasitics and open design issues. Groups prepare their main findings and questions for the joint session. The groups identify their main findings, potential design risks, and questions and prepare these for the joint review session on the 26/11. The design review document should be submitted on the latest 23:59. |
SL |
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4 (48) Thu 26/11 13-15 |
Lecture 14: PCB Design Review Workshop part 2 Common review of observations and questions from the project groups. Discussion of alternative design solutions, critical design decisions, PCB implementation, parasitics and issues to address before the next project stag |
FL
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4 (48) Thu 26/11 15-17 |
Computer lab 4: Support with PCB review findings and Layout Version 2. |
LL/FL |
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4 (48) Fri 27/11 13-15 |
Computer lab 5: Support with PCB Layout Version 2, DFM checks and manufacturing-release files. |
LL/SL |
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4 (48) Sun 29/11 12 23:59 |
Deadline hand-in 4: PCB Layout Version 2 for ordering. Include changes from Version 1, review findings, DFM/producibility checks and released manufacturing files. |
SL |
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5 (49) Tue 1/12 13-15 |
Lecture 15: Product lifetime, mission profile, component stress and derating. |
LL |
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5 (49) Tue 1/12 15-17 |
Computer lab 6: Support with final component selection, BOM freeze and component-model parameters. COMPULSORY round tour of the CASE lab. OBS, bring photo ID and you must have passed the quiz for the CASE lab BEFORE this. |
LL/VR |
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5 (49) Wed 2/12 13:00 |
Deadline hand-in 5: Final BOM for ordering. Include manufacturer part numbers, packages, critical ratings/margins, availability and final component values. |
SL |
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5 (49) Thu 3/12 13-15 |
Study visit Aros Electronics, production line for PCB |
SL |
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5 (49) Thu 3/12 15-17 |
Study visit Aros Electronics, production line for PCB |
SL |
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5 (49) Fri 4/12 13-15 |
Lecture 16: Product lifetime, reliability calculations and design implications. |
PI |
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6 (50) Tue 8/12 13-15 |
Lecture 17: Guest lecture ANSYS – PCB parasitic simulation as preparation for verification. Model the group PCB and extract/estimate switching-loop inductance. |
FL/ Ansys |
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6 (50) Tue 8/12 15-17 |
Lecture 18: Guest lecture ANSYS – compare analytical and simulated PCB parasitics and use the results to predict hardware behaviour. |
FL/ Ansys |
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6 (50) Wed 9/12 23:59 |
Deadline hand-in 6: Final circuit-simulation results with final component values, ANSYS PCB-parasitic results, analytical-to-ANSYS comparison and verification predictions. |
FL/LL |
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6 (50) Thu 10/12 13-15 |
PCB assembly at CASE lab. Record build status, component deviations and assembly observations for the cumulative report. |
SL |
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6 (50) Thu 10/12 15-17 |
PCB assembly at CASE lab. Record build status, component deviations and assembly observations for the cumulative report. |
SL |
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6 (50) Fri 11/12 13-15 |
PCB assembly at CASE lab. Record build status, component deviations and assembly observations for the cumulative report. |
SL |
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6 (50) Fri 11/12 15-17 |
Mounting of the PCB at CASE lab, optional for the ones that can |
SL |
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7 (51) Tue 15/12 13-15 |
PCB test and verification at CASE lab. Execute the approved verification plan and record measurement setup, uncertainty and results. |
SL |
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7 (51) Tue 15/12 15-17 |
PCB test and verification at CASE lab. Compare measured results with requirements, analytical calculations and simulations. |
SL |
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7 (51) Thu 17/12 13-15 |
PCB test and verification at CASE lab. Include switching-node measurements with documented probing method |
SL |
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7 (51) Thu 17/12 15-17 |
PCB test and verification at CASE lab. Include switching-node measurements with documented probing method |
SL |
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7 (51) Fri 18/12 13-15 |
PCB test and verification at CASE lab. Complete calculation–simulation–measurement correlation. |
SL |
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7 (51) Fri 18/12 15-17 |
Test and verification of the PCB at CASE lab, optional for the ones that can |
SL |
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7 (51) Fri 18/12 17:00 |
Deadline hand-in 7: Lifetime and reliability calculation, including mission profile, component stress/derating and design implications. |
PI/LL |
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8 (2) Thu 7/1 23:59 |
Deadline hand-in 8: Final cumulative report, all chapters, including verification plan, measurement results, calculation–simulation–measurement comparison and requirements compliance. |
FL/LL |
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8 (2) Friday 8/1 13:00 |
Deadline hand-in 9: Presentation slides summarising the engineering process, key design decisions, verification evidence and lessons learned. |
SL |
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9 (3) Mon 11/1 08-12 |
Presentations: all groups present their complete design and verification experience to each other. Compulsory for all students. |
SL/FL |
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9 (3) Thu 14/1 8-17 |
Individual oral examination based on the design project, lectures, engineering decisions, simulations and verification results. Each person books a 30 min slot in Canvas. |
SL/FL |
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9 (3) Fri 15/1 8-17 |
Individual oral examination based on the design project, lectures, engineering decisions, simulations and verification results. Each person books a 30 min slot in Canvas. |
SL/FL |
Changes made since the last occasion
- The complete engineering flow is made explicit from requirements to verification.
- The Würth guest lecture is placed on 10 November and focused on translating calculated values into real component design parameters and robust component selection.
- The sessions on 19 November are refocused on switching loops, PCB parasitics, EMI implementation and analytical loop-inductance estimation.
- Early simulation is explicitly defined as circuit simulation supporting dimensioning; ANSYS on 8 December is defined as PCB-parasitic simulation supporting verification.
- Hand-ins are aligned with one cumulative report and require traceability from requirements through calculation and simulation to measurement.
- Verification planning and calculation–simulation–measurement correlation are explicit course activities.
Learning objectives and syllabus
Learning objectives:
- Create and evaluate different steps in a design process from idea to a finished product
- Design a product, with focus on the power electronic parts, from a base of requirements and system knowledge, with respect to the system context and environmental conditions the board is intended to operate in.
- Separate a complex system into fractions to simplify simulations in a practical engineering way
- Analyse and dimension parts of a design to comply with system boundaries
- Interpret and draw electronic schematics, including fundamental understanding and usage of electronic symbols and their connection to the physical layout of the board
- Construct a board layout based on an electronic schematic
- Adapt the product design to environmental condition requirements as well as applicable standards and regulations
- Analyse and compare different types of fault and transient protections.
- Analyse and evaluate a design from an EMI perspective, i.e. how radiated and conducted disturbances propagate and interact with different parts on the PCB and its surrounding.
- Apply producibility and testability in the design
- Discuss how thermal considerations impact different design choices as size/volume, humidity, indoor, outdoor, cooling, price etc.
- Reflect over the value creation made for others
- Plane the project, write a report to document the project and share the experiences with the other students in the course.
- Show an ability to within the project make judgements considering sustainable developments and ethical aspects through:
- Reflection and critical judgement of relevant dimensions of sustainable development
- Handle scientific writing in an ethically defendable way, for instance related to plagiarism and authorship.
- Utilise ethical principles for data acquisition, analysis and result presentation.
Link to the syllabus on Studieportalen.
https://www.chalmers.se/en/education/your-studies/find-course-and-programme-syllabi/course-syllabus/EEN195/?acYear=2024/2025
If the course is a joint course (Chalmers and Göteborgs Universitet) you should link to both syllabus (Chalmers and Göteborgs Universitet).
Examination form
The course consists of two parts:
- Part A, Design exercise + laboratory, 4.0 credits, gradings scale Pass or Fail
- Part B, Oral examination, 3.5 credits, gradings scale Pass or Fail
For Part A, the practical design exercise and laboratory, students shall be present and contribute to the project work and to every hand-in of the cumulative report. Students shall also pass the Writing quiz on Canvas. At each hand-in, the group shall add the new project stage and update earlier sections affected by new calculations, component selections, reviews, simulations or measurements. A contribution report shall be completed for each hand-in. Part A is approved when all submissions, compulsory activities, verification work and the final presentation are approved.
The individual oral examination is based on the project, lectures and engineering discussions during the course, including requirements, calculations, component selection, PCB design, simulation, verification and interpretation of differences between predicted and measured behaviour. The grading scale is Pass or Fail.
The final grade on the course is Pass or Fail. When both the practical design project and the oral examination are graded pass the final grade pass is given for the course.
All deadlines and compulsory things in the course are (these are also shown in the Teaching plan above):
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Study week, Date, Time |
Description |
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2 (46) Mon 9/11 12:00 |
Deadline hand-in 1: Project requirements and specifications, requirement IDs, preliminary verification criteria and Writing quiz. |
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3 (47) Mon 16/11 12:00 |
Deadline hand-in 2: Converter dimensioning, initial circuit simulation and Schematic Version 1. Include all components, correct packages/footprints, critical component design parameters and preliminary component choices; final values are not yet required. |
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4 (48) Mon 23/11 12:00 |
Deadline hand-in 3: PCB Layout Version 1 with correct packages/footprints and test points. Include annotated current/return paths, identified switch loop, analytical loop-inductance estimate, predicted L·di/dt overshoot. The three identified risks connected to the code of ethics for engineers module in Chapter 11 of the report. |
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4 (48) Sun 29/11 23:59 |
Deadline hand-in 4: PCB Layout Version 2 for ordering. Include changes from Version 1, review findings, DFM/producibility checks and released manufacturing files. |
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5 (49) Tue 1/12 15-17 |
COMPULSORY round tour of the CASE lab. OBS, bring photo ID and you must have passed the quiz for the CASE lab BEFORE this. |
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5 (49) Wen 2/12 13:00 |
Deadline hand-in 5: Final BOM for ordering. Include manufacturer part numbers, packages, critical ratings/margins, availability and final component values. |
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6 (50) Wed 9/12 23:59 |
Deadline hand-in 6: Final circuit-simulation results with final component values, ANSYS PCB-parasitic results, analytical-to-ANSYS comparison and verification predictions. |
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7 (51) Fri 18/12 17:00 |
Deadline hand-in 7: Lifetime and reliability calculation, including mission profile, component stress/derating and design implications. |
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8 (2) Thu 7/1 23:59 |
Deadline hand-in 8: Final cumulative report, all chapters, including verification plan, measurement results, calculation–simulation–measurement comparison and requirements compliance. |
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8 (2) Friday 8/1 13:00 |
Deadline hand-in 9: Presentation slides summarising the engineering process, key design decisions, verification evidence and lessons learned. |
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9 (3) Mon 11/1 08-12 |
Presentations: all groups present their complete design and verification experience to each other. Compulsory for all students. |
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9 (3) Thu 14/1 8-17 |
Individual oral examination based on the design project, lectures, engineering decisions, simulations and verification results. Each person books a 30 min slot in Canvas. |
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9 (3) Fri 15/1 8-17 |
Individual oral examination based on the design project, lectures, engineering decisions, simulations and verification results. Each person books a 30 min slot in Canvas. |
Course summary:
| Date | Details | Due |
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